The present invention relates to a semiconductor device, such as a solid-state image pickup device, a manufacturing method thereof, and an electronic apparatus, such as a camera, including the solid-state image pickup device.
As a solid-state image pickup device, an amplification type solid-state image pickup device represented by an MOS, such as complementary metal oxide semiconductor (CMOS), image sensor has been used. In addition, a charge transfer type solid-state image pickup device represented by a charge coupled device (CCD) image sensor has also been used. These solid-state image pickup devices are widely used for a digital still camera, a digital video camera, and the like. In recent years, as solid-state image pickup devices mounted in mobile apparatuses, such as a camera mobile phone and a personal digital assistant (PDA), many MOS image sensors have been used in view of a low power source voltage, a low power consumption, and the like.
The MOS solid-state image pickup device includes a peripheral circuit region and a pixel array (pixel region) in which a plurality of unit pixels, each of which has a photodiode functioning as a photoelectric conversion portion and a plurality of pixel transistors, is arranged in a two-dimensional array. The pixel transistors are each formed of an MOS transistor, and the unit pixel has three transistors, that is, a transfer transistor, a reset transistor, and an amplifier transistor, or four transistors including a selection transistor besides the above three transistors.
Heretofore, as the MOS solid-state image pickup device described above, various solid-state image pickup devices have been proposed in each of which a semiconductor chip having a pixel region in which pixels are arranged and a semiconductor chip in which a logic circuit performing a signal processing is formed are electrically connected to each other to form one device. For example, in Japanese Unexamined Patent Application Publication No. 2006-49361, a semiconductor module has been disclosed in which a backside illuminated image sensor chip having micro pads in individual pixel cells and a signal processing chip which includes a signal processing circuit and micro pads are connected to each other with micro bumps interposed therebetween. In Japanese Unexamined Patent Application Publication No. 2007-13089, a device has been disclosed in which a sensor chip including an image pick-up pixel portion, which is a backside illuminated MOS solid-state image pickup element, and a signal processing chip which includes a peripheral circuit performing signal processing are mounted on an interposer (intermediate substrate). In Japanese Unexamined Patent Application Publication No. 2008-130603, the structure has been disclosed in which an image sensor chip, a thin film circuit board, and a logic circuit chip performing signal processing are provided. In addition, the structure has also been disclosed in which the logic circuit chip is electrically connected to this thin film circuit board, and the thin film circuit board is electrically connected to wire layers through a through-hole via from the rear surface of the image sensor chip.
In Japanese Patent No. 4000507, a solid-state image pickup device has been disclosed in which a solid-state image pickup element mounted on a transparent substrate is provided with a penetration electrode and is electrically connected to a flexible circuit board therethrough. Furthermore, according to Japanese Unexamined Patent Application Publication No. 2003-31785, a backside illuminated solid-state image pickup device has been disclosed in which an electrode penetrating a support substrate is provided.
As shown in Japanese Unexamined Patent Application Publication Nos. 2006-49361 and 2007-13089 and Japanese Patent No. 2008-130603, techniques in which different types of circuits, such as an image sensor chip and a logic circuit, are mounted in combination have been variously proposed. In related techniques, the features thereof are that functional chips used for this purpose are all in an almost finished making state and are formed on one chip so as to be connectable to each other by forming through substrate via holes.
As shown in the related solid-state image pickup device described above, an idea to form a semiconductor device by connecting between different types of chips with a connection conductor penetrating substrates has been proposed. However, since the connection hole has to be formed in a thick substrate while the insulation is ensured, it has been believed that the above idea is difficult to practically realize in consideration of cost economy of manufacturing processes necessary for machining the connection hole and filling a connection conductor therein.
In addition, in order to form a small contact hole having a diameter of approximately 1 μm, the thickness of an upper chip has to be ultimately reduced. In this case, before the reduction in thickness is performed, a complicated step, such as a step of adhering the upper chip to a support substrate, is necessarily performed, and hence the cost is unfavorably increased. Furthermore, in order to fill a connection conductor in a connection hole having a high aspect ratio, a CVD film, such as a tungsten (W) film, having good covering properties has to be used as the connection conductor, and hence a material for the connection conductor is limited.
In order to obtain a manufacturing process which has a superior economic efficiency and which can be easily applied to mass production, the aspect ratio of this connection hole has to be dramatically decreased for easy formation, and in addition, without using particular connection hole machining, a machining technique used in a related wafer manufacturing process is preferably selected.
In addition, in a solid-state image pickup device and the like, it has been desired that an image region and a logic circuit performing signal processing be formed to exhibit sufficient properties thereof and that the performance of the device be improved.
Besides the solid-state image pickup device, also in a semiconductor device having different types of semiconductor integrated circuits, it has been desired that the semiconductor integrated circuits be formed to exhibit sufficient properties thereof and that the performance of the semiconductor device be improved.
Furthermore, in a device in which chips are connected to each other by adhering substrates at the circuit surfaces thereof, in order to perform mounting connection, bonding pads and openings therefor necessarily formed in the vicinity of an interface of the adhesion. However, when the thickness of the substrate is large, such as approximately several hundreds of micrometers, high-cost mounting steps, such as formation of deep holes, formation of lead electrodes, and formation of solder balls, have to be performed.
In addition, since the adhesion surface has a fragile structure as compared to that of another interlayer boundary, when the boundary of the adhesion surface is present under the bonding pad, a stress generated in bonding is concentrated on a fragile portion, and as a result, cracks may be generated from the adhesion surface portion in some cases.
Furthermore, when semiconductor wafers are divided by dicing, cracks may also be generated from the adhesion surface between the substrates in some cases.